This invention relates to a delay circuit and, more particularly, to a programmable delay circuit which is formed of directly coupled inverter elements and which may be constructed as an integrated circuit chip.
Delay circuits are known for establishing a desired time delay to an input electrical signal. Such delay circuits may be characterized as analog delay circuits, such as a coaxial line whose delay is determined by the length of that line, and digital delay circuits, such as cascaded monostable multivibrators, shift registers, or the like, which are capable of imparting delays to pulse signals as a function of the number of such cascaded circuits, the frequency of timing pulses supplied thereto, and the like. While coaxial lines generally provide desirable time delays, such lines often must be of unwieldy lengths, and generally are extremely inconvenient for practical applications. Also, they tend to distort and attenuate the signal which is delayed thereby. Other time delay circuits have been introduced, such as glass delay lines, multi-channel "lumped" delay lines, and the like. However, in these devices, the time delays often are too large for many applications; and inherent time delays thereof are not easily adjusted, or modified. Furthermore, interference due to temperature dependency generally is not easily corrected.
The time delays produced by cascaded monostable multivibrators are a function of the inherent time delay of each such multivibrator. Typically, when such cascaded multivibrators are used to impart a time delay to an input pulse signal, successive pulse signals are spaced apart by a time difference that is at least equal to the overall time delay exhibited by the cascaded multivibrators. This limits the pulse separation which can be used with such delay circuits. Furthermore, the overall temperature dependency of such cascaded multivibrators is relatively high because each individual multivibrator is itself temperature dependent, thus resulting in cumulative temperature-related errors.
The use of a shift register as a time delay circuit also suffers from disadvantages. A shift register generally imparts a time delay to a pulse signal by loading that pulse signal into the shift register in response to a clock pulse, and shifting that pulse signal through the shift register in response to successive clock pulses. The delay exhibited by such a shift register time delay circuit is, thus, a function of the periodicity of the clock pulses and the number of stages included in the shift register. However, since the shift register is loaded in synchronism with the clock pulses, any deviation or time-displacement of the input pulse signal relative to the clock pulses is eliminated. Thus, if the integrity of the relative time of occurrence of such a pulse signal is to be preserved, the use of shift register time delay circuits has a tendency to distort that integrity.
Recently, charge coupled devices (CCD) have been proposed for use as time delay circuits. In a typical charge coupled device, such as a bucket brigade delay line, MOS components are cascaded. Field effect transistors (FETs) function as switches, and such switch-type FETs alternate with FET amplifiers whose gate electrodes exhibit inherent capacitance that is used as a storage device. In operation, a switch-type FET opens to pass an input signal, such as a pulse sample, to be stored at the gate electrode of the next-following FET amplifier. Then, the first switch-type FET is closed and the next-following switch-type FET is opened so as to pass the signal which had been stored at the gate electrode of the FET amplifier. In this manner, successive switches are opened alternately, and in sequence, so as to "ripple" the sampled signal from one FET amplifier to the next. The overall delay of this CCD is a function of the number of FET amplifier stages, the number of FET switches, and the frequency, or periodicity, of the clock signals which are used to open the FET switches in sequence. Generally, the overall delay may be too large for many applications. Also, the delay exhibited by such CCD circuits is not easily controlled, modified or adjusted; and substantially different delays may be exhibited by what otherwise appears to be two identical CCD circuits.